module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    output walk_left,
    output walk_right); //  

    /*
    // parameter LEFT=0, RIGHT=1, ...
    reg state, next_state;

    always @(*) begin
        // State transition logic
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
    end

    // Output logic
    // assign walk_left = (state == ...);
    // assign walk_right = (state == ...);
    */
    
    parameter	NONE = 2'b00;
    parameter	LEFT = 2'b10;
    parameter	RIGHT = 2'b01;
    parameter	BOTH = 2'b11;
    
    reg	[1:0]	state;
    
    always @(posedge clk or posedge areset) begin
        if(areset) begin
            state <= LEFT;
        end
        else begin
            case({bump_left, bump_right})
            	NONE:	state <= state;
                LEFT:	state <= (state == LEFT) ? RIGHT : state;
                RIGHT:	state <= (state == LEFT) ? state : LEFT;
                BOTH:	state <= (state == LEFT) ? RIGHT : LEFT;
        	endcase
        end
    end
    
    assign {walk_left, walk_right} = state;

endmodule
